A program's speed comes down to three numbers: how many instructions it runs, how many clock cycles each one takes on average, and how long a cycle lasts. Pipelines, branch predictors, caches, vector units, multicore chips, and AI accelerators are all attempts to shrink one of those numbers without inflating the others or exceeding the energy budget. Across nine modules and 60 sessions, this collection teaches computer architecture in that quantitative spirit, from instruction sets and the five-stage pipeline through out-of-order execution, the memory hierarchy, GPUs, multicore coherence, warehouse-scale computers, and domain-specific accelerators. Every quantitative session works at least one numerical example step by step, so the reader learns to compute CPU time, speedup, average memory access time, and energy, and to use them to compare two designs. It is written for programmers, engineering students, and self-taught engineers who know basic programming and binary arithmetic and want to understand the hardware their code runs on.
